1. Field of Invention
The present invention relates to a wafer level packaging technology. More particularly, the present invention relates to method for manufacturing Through-Silicon Vias (TSV).
2. Description of Related Art
With the advance of the semiconductor manufacturing technology, more and more devices are integrated into a semiconductor circuit. However, when more devices are involve in a 2-dimensional (2D) semiconductor circuits, it requires more space to accommodate the devices and needs longer wires to connect thereto. Besides, resistance-capacitance (RC) delay may occur and power consumption should be increased significantly, both may adversely affect the performance of the semiconductor circuit.
To resolve these problems, a system-on-chip (SoC) and/or system-in-package (SiP) technology are provided, wherein a 2D or 3-dimensional (3D) packaging structure is adopted to integrate devices in a single die. However, the conventional SoC and/or SiP technology still has drawbacks. Hence the 2D or 3D packaging technology still utilizes bonding wires or contact pads to connect the integrated devices, thus when more and more device is integrated on the die, the size of the die would be significantly increased and the performance thereof should be deteriorated.
Currently, a new 3D packaging technology-TSV is introduced to improve the aforementioned problems, wherein a TSV is an interconnection penetrating through at least one dielectric layer of a wafer or a die to provide an electrical contact to devices vertically aligned with each other and disposed in the wafer or the die. Hence the vertical interconnection can reduce the contact distance, thus the circuit complexity of the package structure would be reduced, meanwhile the line width of the interconnections can be increased. Accordingly the speed of the devices should be enhanced and the power consumption should be reduced.